The present invention relates to a non-volatile memory device and the like which includes a plurality of non-volatile memory chips and a non-volatile memory controller equipped with an interface for executing I/O processes of data to and from the non-volatile memory chips.
Conventionally, non-volatile memory devices including a plurality of non-volatile memory chips have been known. A NAND-type flash memory chip has been known as an example of a non-volatile memory chip.
NAND-type flash memory chips are available as a wide variety of products and flash memory chips of different types may conceivably be mounted to a non-volatile memory device. When such a configuration is envisaged, various parameters in interfaces (flash I/Fs) respectively provided in a flash memory controller which controls I/O processes to and from the flash memory chips inside the non-volatile memory device and in the flash memory chips must be optimized for each type of the flash memory chips.
When optimizing the various parameters in a flash I/F, for example, a transmission waveform produced by the flash I/F may conceivably be evaluated with an oscilloscope to retrieve optimal parameters.
For example, as a method of optimizing parameters of an I/F for performing transmission between LSIs, a technique has been known, which involves preparing a table of power-supply voltage and a configuration parameter for each of a plurality of operating frequency bands and selecting a configuration parameter from the table (for example, refer to Japanese Patent Application Publication No. 2011-41109).